IEEE A-SSCC 2019

IEEE Asian Solid-State Circuits Conference

 Call for Papers

Download the Call for Papers here.

Conference Theme:Silicon Systems for Next Smart Society

Solid-state circuits have improved our lives for more than 50 years. There is no doubt that we have benefited from a wide variety of electronic equipment such as mobile computing devices, car electronics and digitalized social infrastructures. Rapid progress of artificial intelligence accelerated by deep learning, in conjunction with big data collected by IoT, may change our lives non-linearly. As a consequence, we will use smarter mobile devices, drive or be driven by, smarter cars and live on a smarter infrastructure, leading to totally different quality of life. There, we will face new challenges and opportunities for silicon systems, which our community should overcome and take advantage of.

The IEEE A-SSCC 2019 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields. The conference is supported by the IEEE Solid-State Circuits Society and will be held in Asia. Further details on the conference and paper submission guidelines and templates will be available at the A-SSCC official website http://www.asscc.org/ (or http://www.a-sscc2019.org/) around the beginning of April 2019.

Paper Submission

Prospective authors are invited to submit four-page or two-page manuscripts, including figures, tables and references, to the official A-SSCC 2019 website.The two-page submission could include two-page supplements with figures and figure captions.Supplementary figures should not be referred to in the text of the paper. For further details, see the A-SSCC Website. Papers are solicited in the following categories:

Regular Session
  1. Analog Circuits & Systems: Amplifiers, comparators, switched capacitor circuits, continuous-time & discrete-time filters, voltage/current references; DC-DC converters, power-control circuits; IF/baseband analog circuits, AGC/VGA; non-linear analog circuits.
  2. Data Converters: Nyquist-rate and oversampling A/D, D/A converters, time-to-digital converters, and capacitance-to-digital converters; sub-circuits for data converters including sample-and-hold circuits, calibration circuits, etc.
  3. Digital Circuits & Systems: Design, fabrication, and test of digital VLSI systems; high-speed low-power digital circuits, power-reduction and management methods for digital VLSI, ultra-low-voltage and sub-threshold logic design; leakage reduction techniques; clock distribution, I/O circuits, reconfigurable logic-array circuits; supply/substrate noise measurement and cancellation for digital VLSI, variation and fault-tolerant circuits.
  4. SoC & Signal Processing Systems: System-on-chip(including 3D integration), microprocessors, network processors, baseband communication processing system & architectures, system-level power management; multimedia and recognition processing systems; cryptographic, security, machinelearning, deep-learning, and neuromorphic circuits and systems; bio-medical/neural-network processors and sensor network systems.
  5. RF: Receivers/transmitters/transceivers for wireless systems; narrowband RF, ultra-wideband and millimeter-wave circuits; circuits and building-blocks including RF front-end, LNA, mixer, power amplifiers, VCOs, frequency synthesizers, RF filters, RF switches, power detectors, active antennas.
  6. Wireline: Receivers/transmitters/transceivers for wireline systems; optical/electrical data links and backplane transceivers; power-line communication; clock generation circuits, PLL, DLL, spread-spectrum clock generation; building blocks for high-speed wireline communication; analog-digital mixedmode circuits.
  7. Emerging Technologies and Applications: Advanced system designs and circuit solutions for technologies and applications including state-of-the-art devices and packaging technologies; flexible and printable electronics;silicon photonices;smart sensors and transducers; MEMS for analog, RF, and sensor applications; image sensors and displays; energy harvesting systems; transceiver systems; medical/bio-electronics/bio-inspired chip design,artificial intelligent system,and cryogenic circuits and systems.
  8. Memory: Volatile and Non-volatile memory; new memory designs for 3D/2D architectures, emerging devices such as resistive-/phase change-/magnetic- /ferro-electric- memory devices; data storage and multi-bit-cell memory design; cache-memory system, multi-port memory, memory subsystem, processing in memory, and CAM design; yield-enhancing and ECC techniques; memory testing and built-in self-test.
  9. FPGA: Novel algorithm and/or architecture for integrated circuits validated by FPGA implementation. The authors of accepted papers are required to participate in demo sessions.
Special Session
  1. Industry Program: This special category accepts only papers based on state-of-the-art industrial products. Strong emphasis on systems realized by silicon chips is encouraged. The papers should cover architecture, circuits, process technology, packaging and testing, includin g characterization results, die and system photos, as well as product demos.
  2. Student Design Contest: A student design contest is held among the accepted papers with system prototypes or measurement results of which operations can be demonstrated on-site. Refer to the web for further information.

Papers related to integrated circuits for next smart society are highly solicited. Papers on low-power and/or low-voltage approaches, signal integrity, noise, test, and manufacturability for all the above categories are welcomed. Measurement results are highly recommended, especially for analog, and RF categories. Design methodologies for SiP, and SoC are included in the scope of the conference; the papers only describing CAD tools and CAD algorithms are not considered. Authors must follow detailed instructions provided within the “Authors” section of the website, including the Authors’ Gu ide and Prepublication Policy. The technical content beyond the abstract of the accepted paper must not be announced, published, or in a ny way put in the public domain prior to the Conference. Extended versions of selected papers from the Conference will be published in a Special Issue of the IEEE Journal of Solid-State Circuits.

Important dates

Paper submission
Final paper submission

June 2, 2019, 20:00 (GMT) September 8, 2019

Acceptance notification

August 5, 2019

Steering Committee Chair Tadahiro KURODA, Keio Univ., Japan kuroda [at] elec.keio.ac.jp
Conference Chair Rui MARTINS, Univ. of Macau, China rmartins [at] um.edu.mo
Organizing Committee Chair Seng-Pan (Ben) U, Univ. of Macau & Synopsys Macau, China benspu [at] ieee.org
Organization Committee Vice Co-Chairs Leibo LIU, Tsinghua University, China liulb [at] tsinghua.edu.cn
Howard LUONG, HKUST, Hong Kong, China eeluong [at] ee.ust.hk
Technical Program Committee Chair Mototsugu HAMADA, Keio Univ., Japan hamada [at] kuroda.elec.keio.ac.jp
Co-Chair Robert Chen-Hao CHANG, Nat’l Chung Hsing Univ., Taiwan chchang [at] nchu.edu.tw
Vice-Chair Jun DEGUCHI, Toshiba Memory, Japan jun.deguchi [at] toshiba.co.jp
Vice-Co-Chair Po-Hung CHEN, National Chiao Tung Univ., Taiwan hakko [at] nctu.edu.tw